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First name:  Mateusz Piotr
Surname:  Nowak
Title:  PhD
Team:  Computer Systems Modelling and Performance Evaluation Group
Position:  asisstant professor
E-mail:  picture
Phone:  +48 32 2317319 w. 202
 
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 GG 511718
 
bulletPublications
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 [1] Reducing the Number of States for Markovian Model of Optical Slotted Ring Network, 2010
[2] QoS management for multimedia traffic in synchronous slotted-ring OPS networks, 2010
[3] Synchronisation concept for distributed simulation of networks with packet loss, 2009
[4] Simulation and Analytical Evaluation of a Slotted Ring Optical Packet Switching Network, 2009
[5] Priority Registers Mechanism for fair access to ring-type OPS network, 2009
[6] Concept of new synchronisation method for wireless networks distribiuted simulation, 2008
[7] Parallel simulation of networks with packet loss, 2007
[8] Methods of reducing the number of synchronisation messages for event-driven simulation, 2006
[9] Dynamiczne zarządzanie realizacją programów równoległych w środowisku rozproszonym, 2006
[10] Samoorganizacja w nanosystemach, 2004
[11] Metody ograniczania liczby komunikatów synchronizujących w symulacji rozproszonej, 2004
[12] Improvement of synchronisation and load balancing for dsim simulator, 2004
[13] Selforganization in nanosystems of informatics, 2004
[14] Wyrównywanie obciążenia w warunkach intensywnej komunikacji., 1999
[15] Distributed image-processing algorithms in a network of workstations, 1998
[16] Data exchange organisation in distributed applications based on message passing in a network of workstations, 1998
[17] Systemy komunikacyjne w automatyzacji procesów wytwarzania, 1997
[18] FTAM – protokół przesyłu i zarządzania plikami, 1997
[19] Porównanie cech środowisk PVM i MPI, 1997
[20] Systemy wizualizacji algorytmów wspomagające badania naukowe, 1996
 
bulletProjects
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 [1] Methods and models for control of congestion and performance evaluation of mechanisms of qualities of services in the next generation internet (własny N517 025 31/2997, 2006-2008)
[2] Study of possibility based on the long term theoretical knowledge of the JPEG2000 algorithms and his implementation in the DSP TMS320C6414 and FPGA from Xilinx (zlecony, 2005-2007)
[3] Study of possibility to use the JPEG2000 algorithm on the on the evaluation embedded system (IE64/1GHz) (zlecony, 2004-2005)
[4] Study of possibility of porting Active-VHDL software from MS-Windows environment to UNIX environment (zlecony, 1998)
[5] (zamawiany PBZ-31-05, 1995-1996)
[6] (promotorski 4 T11C 032 25, 1999)
[7] (własny 8 T11C 00614, 1999)
 
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